- ... checker.1
- The
material presented in this paper is self-contained. This paper is readable
with ordinary efforts for someone with some background in formal methods.
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- ...
total.2
- A transition relation
is
total if and only if for each state
there exists a state
such that
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- ...[23,28,51].3
- This is almost
true. However, the very first implementation of the CESAR tool was a
symbolic model checker. See [52] for more details.
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- ...
variables.4
- For non boolean state variables a boolean encoding
can be performed.
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- ... shell.5
- The
output was slightly modified to make it more readable.
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- ... built.6
- This file can be generated
by hand by the user or automatically by activating the
automatic variable ordering to reduce the size of the BDDs
and saving the results with the write_order
command.
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- ....7
- This has
the effect that for examples the BDD representing the encoding of
st =
c is only in terms of the boolean variables
st0 and
st1.
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- ...8
- If
is a
set, then with
we mean the complement set.
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- ...INVAR9
- INVAR specifies time invariants using
propositional formulas.
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- ...
specification10
- In the NUSMV input language this specification
is written as SPEC AG(alpha -> ABF 0..4 beta)
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- ...
fairness,11
- A typical fairness property is ``if a process is infinitely
often executable then it is infinitely often executed'', that corresponds to
the LTL formula: ``
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- ... model.12
-
Other model checkers [6,41] are able to perform
LTL model checking. In VIS [6], for example, it is
possible to perform LTL model checking by using the language
emptiness feature [60], but the user has to write by hand the
automaton representing the acceptance condition of the LTL formula,
and for each formula a different input file has to be generated and
the computation must restart from scratch.
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- ... extended.13
- A similar
philosophy of developing an open platform is advocated by the authors of the
CADP tool-box [34].
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- ...
netlist14
- A netlist is a representation of a design at the structural
level. A FSM can be viewed as a behavioral description of the design. A
netlist is much closer to the implementation of the design than a simple
FSM. A netlist is essentially the data structure used by many logic synthesis
tools ,like VIS[6], to internally represent designs derived from
HDL descriptions.
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- ...Purify15
- More information on this tool can be found at the url
``|http://www.pureatria.com|''.
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- ... tool.16
- More information about the ext documentation tool can
be found at the url ``|http://alumnus.caltech.edu/ sedwards/ext|''
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- ...
memory17
- It is the maximum amount of memory allocated during state
space generation and search, namely, the amount of memory allocated since the
program starts to the end of the computation before freeing all the memory
allocated.
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- ...[20,21].18
- See [37] for an
introduction and a survey of planning as model checking.
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